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Hi-performance Regulator IC Series for PCs
Nch FET Ultra LDOs for Desktop PCs Chipsets with Power Good
BD3540NUV, BD3541NUV
No.09030EBT04
Description The BD3540NUV, BD3541NUV low-voltage output linear 1ch series chipset regulator IC operates from a very low input supply, and offers ideal performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to minimize the input-to-output voltage differential to the ON resistance (RON=200m 400m) level. By lowering the dropout voltage in this way, the regulator realizes high current output (Iomax=0.5A1.0A) with reduced conversion loss, and thereby obviates the switching regulator and its power transistor, choke coil, and rectifier diode. Thus, the BD3540NUV, BD3541NUV are designed to enable significant package profile downsizing and cost reduction. An external resistor allows the entire range of output voltage configurations between 0.65 and 2.7V, while the NRCS (soft start) function enables a controlled output voltage ramp-up, which can be programmed to whatever power supply sequence is required. Features 1) High-precision voltage regulator(0.65V1%) 2) Built-in VCC undervoltage lockout circuit 3) NRCS (soft start) function reduces the magnitude of in-rush current 4) Internal Nch MOSFET driver offers low ON resistance 5) Built-in current limit circuit 6) Built-in thermal shutdown (TSD) circuit 7) Variable output 8) Small package VSON010V3030 : 3.0x3.0x1.0(mm) 9) Tracking function Applications Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances Line-up It is available to select power supply voltage and maximum output voltage. Maximum Output Voltage Package Vcc=5V 0.5A BD3540NUV VSON010V3030 1.0A BD3541NUV
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1/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Absolute maximum ratings BD3540NUV, BD3541NUV Parameter Input Voltage 1 Input Voltage 2 Enable Input Voltage PGOOD Input Voltage Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Operating Temperature Range Storage Temperature Range Junction Temperature Symbol VCC VIN Ven VPGOOD Pd1 Pd2 Pd3 Topr Tstg Tjmax Limit BD3540NUV +6.0 *1 +6.0 *
1
Technical Note
BD3541NUV
Unit V V V V W W W
-0.3+6.0 +6.0*1 0.70*2 1.27*2 3.03
*2
-10+100 -55+150 +150
*1 Should not exceed Pd. *2 Reduced by 5.6mW/ for each increase in Ta25 (when mounted on a 74.2mmx74.2mmx1.6mm glass-epoxy board, 1-layer) On less than 0.2% (percentage occupied by copper foil. *3 Reduced by 10.1mW/ for each increase in Ta25 (when mounted on a 74.2mmx74.2mmx1.6mm glass-epoxy board, 1-layer) On less than 7.0% (percentage occupied by copper foil. *4 Reduced by 24.2mW/ for each increase in Ta25 (when mounted on a 74.2mmx74.2mmx1.6mm glass-epoxy board, 1-layer) On less than 65.0% (percentage occupied by copper foil.
Operating Voltage(Ta=25) BD3540NUV, BD3541NUV Parameter Input Voltage 1 Input Voltage 2 Output Voltage PGOOD Input Voltage Output Voltage Setting Range Enable Input Voltage
Symbol VCC VIN IO VPGOOD Vo Ven
Min. 3.0 0.95 -0.3 VFB 0 BD3540NUV 0.5
Max. 5.5 VCC-1
*1*5
Unit V V BD3541NUV 1.0 A V V V
5.5 2.7 5.5
*5 VCC and VIN do not have to be implemented in the order listed. *This product is not designed for use in radioactive environments.
Attention : About this document The official specification of this product (BD354XNUV) is the Japanese version. This translation is intended only as a reference to understand the official version. If there are any differences between the Japanese and this translated version, the official Japanese version takes priority.
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2/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Electrical Characteristics (Unless otherwise specified, Ta=25, VCC=5V, Ven=3V, VIN=1.7V, R1=3.9K, R2=3.3K) Parameter Bias Current VCC Shutdown Mode Current Output Voltage Output Voltage Temperature Coefficient Feedback Voltage 1 Feedback Voltage 2 Load Regulation Line Regulation 1 Line Regulation 2 Standby Discharge Current [ENABLE] Enable Pin Input Voltage High Enable PinInput Voltage Low Enable Input Bias Current [NRCS] NRCS Charge Current NRCS Standby Voltage [UVLO] VCC Undervoltage Lockout Threshold Voltage VCC Undervoltage Lockout Hysteresis Voltage [PGOOD] Low-side Threshold Voltage High-side Threshold Voltage PGDLY charge current Ron [AMP] Minimum dropout voltage BD3540NUV BD3541NUV dVo dvo 200 200 300 300 mV mV Inrcs VSTB 14 20 0 26 50 A mV Symbol ICC IST VOUT Tcvo VFB1 VFB2 Reg.L Reg.l1 Reg.l2 Iden Limit Min. 0.643 0.637 1 Typ. 0.7 0 1.200 0.01 0.650 0.650 0.5 0.1 0.1 Max. 1.0 10 0.657 0.663 10 0.5 0.5 Unit mA A V %/ V V mV %/V %/V mA Ven=0V
Technical Note
Condition
Tj=-10 to 100 (BD3540NUV Io=0A to 0.5A) (BD3541NUV Io=0A to 1.0A) VCC=3.0V to 5.5V VIN=1.5V to 3.3V Ven=0V, Vo=1V
Enhi Enlow Ien
2 0 -
7
VCCx0.15 10
V V A Ven=3V Vnrcs=0.5V Ven=0V
VccUVLO Vcchys
2.3 50
2.5 100
2.7 150
V mV
Vcc:Sweep-up Vcc:Sweep-down
VTHPGL VTHPGL IPGDLY RPG
VOx0.87 VOx1.07 1.4 30
VOx0.9 VOx1.1 2.0 75
VOx0.93 VOx1.13 2.6 150
V V A Io=0.5A, VIN=1.2V, Ta=-10 to 100 Io=1.0A, VIN=1.2V, Ta=-10 to 100
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3/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Reference Data(BD3540NUV)
Technical Note
Vo 50mV/div 13mV
Vo 50mV/div Vo 29mV 50mV/div 38mV
Io 0.5A/div
0.5A
Io 0.5A/div 0.5A
Io 0.5A/div
0.5A
Io=0A1A/sec
t(10sec/div)
Io=0A1A/sec
t(10sec/div)
Io=0A1A/sec
t(10sec/div)
Fig.1 Transient Response (00.5A) Co=100F, Cfb=1000pF
Fig.2 Transient Response (00.5A) Co=47F, Cfb=1000pF
Fig.3 Transient Response (00.5A) Co=22F, Cfb=1000pF
Vo 50mV/div
13mV
Vo 50mV/div
25mV
Vo 50mV/div 35mV
Io 0.5A/div
0.5A
Io 0.5A/div
0.5A
Io 0.5A/div
0.5A
Io=1A0A/sec
t(100sec/div)
Io=1A0A/sec
t(100sec/div)
Io=1A0A/sec
t(100sec/div)
Fig.4 Transient Response (0.50A) Co=100F, Cfb=1000pF Reference Data(BD3541NUV)
Fig.5 Transient Response (0.50A) Co=47F, Cfb=1000pF
Fig.6 Transient Response (0.50A) Co=22F, Cfb=1000pF
Vo 50mV/div 42mV
Vo 50mV/div 53mV
Vo 50mV/div 59mV
Io 1A/div 1.0A
Io 1A/div 1.0A
Io 1A/div 1.0A
Fig.7 Transient Response (01.0A) Co=100F, Cfb=1000pF
Fig.8 Transient Response (01.0A) Co=47F, Cfb=1000pF
Fig.9 Transient Response (01.0A) Co=22F, Cfb=1000pF
Vo 50mV/div
42mV
Vo 50mV/div
51mV
Vo 50mV/div
57mV
Io 1A/div
1.0A
Io 1A/div
1.0A
Io 1A/div
1.0A
Fig.10 Transient Response (1.00A) Co=100F, Cfb=1000pF
Fig.11 Transient Response (1.00A) Co=47F, Cfb=1000pF
Fig.12 Transient Response (1.00A) Co=22F, Cfb=1000pF
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4/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Reference Data(BD3540NUV)
Technical Note
VCC VCC Ven Ven VIN VIN
VCC
Ven
VIN Vo
Fig.19 Waveform at output start
Fig.20 Waveform at output OFF
Fig.21 Input sequence
VCC
VCC
VCC
Ven
Ven
Ven
VIN Vo
VIN Vo
VIN Vo
Fig.22 Input sequence
Fig.23 Input sequence
1.25
Fig.24 Input sequence
VCC
VCC
1.23 1.21 1.19 1.17 1.15
Ven
Ven
VIN
VIN
Vo(V)
Vo VINVenVCC
Vo VenVINVCC
-10
10
30
50 Ta()
70
90
Fig.25 Input sequence
Fig.26 Input sequence
Fig.27 Ta-Vo (Io=0mA)
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5/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Reference Data(BD3540NUV)
0.70 0.65 0.60 0.55 ICC(mA) 0.50
Technical Note
0.10 0.08 0.06 ICC(uA) 0.04 0.02
1.70 1.65 1.60 IIN(mA) 1.55 1.50 1.45
0.45 0.40 0.35 0.30 0.25 0.20 -10 10 30 50 Ta() 70 90 100 100
0.00 -60 -30 0 30 60 Ta() 90 120 150
1.40 -10 30 Ta() 70 100
Fig.28 Ta-ICC
Fig.29 Ta-ISTB
Fig.30 Ta-IIN
30 25
INRCS(uA) INRCS(uA) INRCS(uA)
20 IIN (u A ) 15 10 5 0 -60 -30 0 30 Ta() 60 90 120 150
20 20 20 19 19 19 18 18 18 17 17 17 16 16 16 15 15 15 -10 -10 -10
IFB(nA) IFB(nA)
10 10 10 30 30 30 50 50 50 Ta() Ta() Ta() 70 70 70 90 90 100 90 100
25 25 25 24 24 24 23 23 23 22 22 22 21 21 21
20 20 15 15 10 10 5 5 0 0 -5 -5
-10 -10 -15 -15 -20 -20 -10 -10 90 100 90 100
10 10
30 30
50 50 Ta() Ta()
70 70
Fig.31 Ta-IINSTB
Fig.32 Ta-INRCS
Fig.33 Ta-IFB
10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 -10 -10 10 10 30 30 50 50 Ta() Ta()
7070
RON(m) RON(m)
RON(m)
10 10 30 30 30 50 50 50 Ta() Ta() Ta() 70 70 70 90 90 100 90 100
Ien(uA) Ien(uA)
180 170 150 170 160 140 160 150 150 130 140 140 130 120 130
200 190 180 170 160 150 140 130 120 2 4 Vcc(V) 6 8
120 120 110 110 110 100 100
90 90
100 90 90 100
-10 -10
Fig.34 Ta-Ien
Fig.35 Ta-RON (VCC=5V/Vo=1.2V)
Fig.36 VCC-RON
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6/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Block Diagram
VCC
C1 1 UVLO CL Current Limit
Technical Note
VIN
5
VIN
C2
EN
2
Reference Block
VCC
Thermal Shutdown TSD NRCS
CL UVLO TSD
6
Vo CFB Vo FB R1 C3 R2
Vo
EN
7 8
Power Good
NRCS
9
10
GND
4
CNRCS
PGDLY CPGDLY
3
PG
Pin Function Table PIN No. 1 2 3 4 5 6 7 8 9 10 PIN name VCC EN PG PGDLY VIN VO VO FB NRCS GND PIN Function Power supply pin Enable input pin Power Good pin Power Good Delay capacitor connection pin Input voltage pin Output voltage pin Output voltage pin Reference voltage feedback pin In-rush current protection (NRCS) capacitor connection pin Ground pin
Pin Layout VSON010V3030
3.00.1
3.00.1
BD3 54 x
Lot No.
1.0Max.
S
0.08 S
Lot No.
C0.25
0.40.1
2.00.1
1 5
1.20.1
0.02 +0.03 -0.02 (0.22)
(Unit : mm)
10
6
0.5
0.5
0.25 +0.05 -0.04
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7/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Technical Note
Operation of Each Block AMP This is an error amp that compares the reference voltage (0.65V) with Vo to drive the output Nch FET (Ron=100m 400m). Frequency optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is OFF, or when UVLO is active, output goes LOW and the output of the NchFET switches OFF. EN The EN block controls the regulator's ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is maintained at 0A, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the NRCS pin Vo, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no electrical connection is required (e.g., between the VCC pin and the ESD prevention Diode), module operation is independent of the input sequence. UVLO To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF, and (like the EN block) discharges NRCS and Vo. Once the UVLO threshold voltage (TYP2.5V) is reached, the power-on reset is triggered and output continues. CURRENT LIMIT When output is ON, the current limit function monitors the internal IC output current against the parameter value (2.0A or more:BD3540NUV). When current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent state is eliminated, output voltage is restored to the parameter value. NRCS (Non Rush Current on Start-up) The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as a 20A (TYP) constant current source to charge the external capacitor. Output start time is calculated via formula (1) below. t=C 0.65V 20A (1)
Tracking sequence is available by connecting the output voltage of external power supply instead of external capacitor. And then, ratio-metric sequence is also available by changing the resistor division ratio of external power supply output voltage. (See the next page) TSD (Thermal Shut down) The shutdown (TSD) circuit automatically switches output OFF when the chip temperature gets too high, thus serving to protect the IC against "thermal runaway" and heat damage. Because the TSD circuit is provided to shut down the IC in the presence of extreme heat, in order to avoid potential problems with the TSD, it is crucial that the Tj (max) parameter not be exceeded in the thermal design. VIN The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical connection (such as between the VCC pin and the ESD protection Diode) is necessary, VIN operates independent of the input sequence. However, since an output NchFET body Diode exists between VIN and Vo, a VIN-Vo electric (Diode) connection is present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from Vo. PGOOD It outputs the output voltage (Vo). PGOOD pin (open drain) is used to pull up the 100k resistor. PGOOD will be judged HIGH between the FB voltage 0.585V(TYP) to 0.715V(TYP), and will be judged LOW if the voltage is out of range. PGDLY It is available to set PGOOD output delay. PGDLY pin should be connected to 100pF capacitor. PGOOD delay time id determined by the following formula. tpgdly= C(pF)x0.75 Ipgdly (A) (sec)
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8/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Timing Chart EN ON/OFF VIN
Technical Note
VCC
EN
0.65V(typ)
NRCS
Startup
Vox0.9V(typ)
Vo
40uS(typ@ C=100pF)
PGOOD t VCC ON/OFF VIN
UVLO Hysteresis
VCC
EN
0.65V(typ)
NRCS
Startup
Vo
40s (typ@100pF)
PGOOD Tracking sequence
1.7V Output 1.2V Output (R1=3.9k, R2=3.3k)
t
DC/DC NRCS Vo 1.7V V0 R2 1.2V 3.3k FB 3.9k
Tracking sequence
1.7V 1.2V
R1
Ratio-metric sequence www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
9/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Evaluation Board BD354XNUV Evaluation Board Schematic
Technical Note
BD354XNUV
BD354XNUV Evaluation Board Standard Component List Component Rating Manufacturer U1 C1 C10 R8 C5 1uF 0.01uF 0 22uF ROHM MURATA MURATA KYOCERA Product Name BD354XNUV GRM188B11A105KD GRM188B11H103KD Jumper CM32X5R226M10A Component Rating Manufacturer C2 C13 R1 R2 R4 22uF 1000pF 3.9k 3.3k 100k KYOCERA MURATA ROHM ROHM ROHM Product Name CM32X5R226M10A GRM188B11H102KD MCR03EZPF3301 MCR03EZPF3901 MCR03EZPF
BD354XNUV Evaluation Board Layout (2nd layer and 3rd layer are GND Line.)
Silkscreen
TOP Layer
Bottom Layer
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10/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Recommended Circuit Example
VCC 1 10 GND 2 9
Technical Note
C1
EN VCC
R4
3
8
R1 FB
C4
R5
4
7
R2
C5 VOUT1(1.2V)
C6
5
6
C3
VIN
C2
Component
Recommended Value
Programming Notes and Precautions IC output voltage can be set with a configuration formula using the values for the internal reference output voltage (VFB)and the output voltage resistors (R1, R2). Select resistance values that will avoid the impact of the VREF current (100nA). The recommended total resistance value is 10K. To assure output voltage stability, please be certain the VOUT1 pins and the GND pins are connected. Output capacitors play a role in loop gain phase compensation and in mitigating output fluctuation during rapid changes in load level. Insufficient capacitance may cause oscillation, while high equivalent series reisistance (ESR) will exacerbate output voltage fluctuation under rapid load change conditions. While a 22F ceramic capacitor is recomended, actual stability is highly dependent on temperature and load conditions. Also, note that connecting different types of capacitors in series may result in insufficient total phase compensation, thus causing oscillation. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VCC) input pins. If the impedance of this power supply were to increase, input voltage (VCC) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 1F capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VIN) input pins. If the impedance of this power supply were to increase, input voltage (VIN) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 22F capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush current from going through the load (VIN to VO) and impacting output capacitors at power supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the UVLO function is deactivated. The temporary reference voltage is proportionate to time, due to the current charge of the NRCS pin capacitor, and output voltage start-up is proportionate to this reference voltage. Capacitors with low susceptibility to temperature are recommended, in order to assure a stable soft-start time. This component is employed when the C3 capacitor causes, or may cause, oscillation. It provides more precise internal phase correction. It is pull-up resistance of Open Drain pin. 100k is recommended. It is recommended that a resistance (several k to several 10k) be put in R4, in case negative voltage is applied in EN pin.
R1/R2
3.9k/3.3k
C3
22F
C1
1F
C2
22F
C4
0.01F
C5
-
R5 R4
100k Several k several 10k
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11/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Input-Output Equivalent Circuit Diagram
VCC VCC 1k 1k
Technical Note
NRCS
1k 1k
VIN
1k
10k 1k
10k
VCC VCC VFB 100k 100k 20pF 1k EN 350k
1k VO1 VO2 50k 1k
10k
Reference landing pattern
MIE E3
e
D3
L2
(Unit : mm) Lead pitch e 0.65 central pad length D3 3.00 Lead pitch MIE 2.50 central pad pitch E3 1.90 landing length l2 0.40 landing pitch b2 0.35
*It is recommended to design suitable for the actual application.
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b2
12/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Technical Note
Notes for Use 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 3. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 5. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 6. Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit: Latch type). The thermal shutdown circuit (TSD circuit: Latch type) is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit isassumed. TSD ON temperature [](typ.) 175 Hysteresis temperature [] (typ.) 15
7. Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. 8. Output voltage resistance setting (R1, R2) Output voltage resistance is adjusted with resistor R1 and R2. This IC is calculated as VFBx(R1+R2) / R1. Total 10k is recommended so that the output voltage is not affected by the VFB bias current. 9. Output capacitors (C3) To assure output voltage stability, please be certain the VO1, VO2, and VO3 pins and the GND pins are connected. Output capacitors play a role in loop gain phase compensation and in mitigating output fluctuation during rapid changes in load level. Insufficient capacitance may cause oscillation, while high equivalent series resistance (ESR) will exacerbate output voltage fluctuation under rapid load change conditions. While a 47uF ceramic capacitor is recommended, actual stability is highly dependent on temperature and load conditions. Also, note that connecting different types of capacitors in series may result in insufficient total phase compensation, thus causing oscillation. In light of this information, please confirm operation across a variety of temperature and load conditions. 10. Input capacitors setting (C1, C2) Input capacitors reduce the impedance of the voltage supply source connected to the (VCC, VIN) input pins. If the impedance of this power supply were to increase, input voltage (VCC, VIN) could become unstable, leading to oscillation or lowered ripple rejection function. Stability highly depends on the input power supply characteristic and the substrate wiring pattern. Please confirm operation across a variety of temperature and load conditions.
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13/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Technical Note
11. NRCS pin capacitors setting (Cnrcs) The Non Rush Current on Startup (NRCS) function is built in the IC to prevent rush current from going through the load (VIN to VO) and impacting output capacitors at power supply start-up. The constant current comes from the NRCS pin when EN is HIGH or the UVLO function is deactivated. The temporary reference voltage is proportionate to time, due to the current charge of the NRCS pin capacitor, and output voltage start-up is proportionate to this reference voltage. To obtain a stable NRCS delay time, capacitors with low susceptibility to temperature are recommended. 12. Input pins (Vcc, VIN, EN) This IC's EN pin, VIN pin, and VCC pin are isolated, and the UVLO function is built in the VCC pin to prevent undervoltage lockout. It does not depend on the Input pin order. Output voltage starts up when VCC and EN reach the threshold voltage. However, note that when putting in VIN pin lastly, VO may result in overshooting. 13. Heat sink (FIN) Since the heat sink (FIN) is connected to with the Sub, short it to the GND. It is possible to minimize the thermal resistance by soldering it to substrate. Please solder properly. 14. Please add a protection diode when a large inductance component is connected to the output terminal, and reverse-polarity power is possible at start-up or in output OFF condition. 15. Short-circuits between pins and mounting errors Please be sure to install the IC in correct position and orientation. Mounting errors, such as incorrect positioning or orientation, or connecting of the power supply in reverse polarity can also destroy the IC. Short-circuit between pins or pin and the power supply, or between ground may also damage to the IC.
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14/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Technical Note
Heat Loss Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed temperature limits, and thermal design should allow sufficient margin from the limits. 1. Ambient temperature Ta can be no higher than 100. 2. Chip junction temperature (Tj) can be no higher than 150. Chip junction temperature can be determined as follows: Calculation based on ambient temperature (Ta) Tj=Ta+j-axW Reference values j-a:VSON010V3030 178.6/W 1-layer substrate (copper foil density 0.2%) 98.4/W 1-layer substrate (copper foil density 7%) 41.3/W 2-layer substrate (copper foil density 65%) 3 Substrate size: 70x70x1.6mm (substrate with thermal via) It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in the inner layer (in using multiplayer substrate). This package is so small (size: 3.0mmx3.0mm) that it is not available to layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below). enable to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the number is designed suitable for the actual situation.).
Most of the heat loss that occurs in the BD354XNUV is generated from the output Nch FET. Power loss is determined by the total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the BD354XNUV) make certain to factor conditions such as substrate size into the thermal design. Power consumption (W) = Input voltage (VIN)- Output voltage (Vo) (VoVREF) xIo(Ave)
Example) Where VIN=1.7V, VO=1.2V, Io(Ave) = 1A, Power consumption (W) = 1.7(V)-1.2(V) x1.0(A) = 0.5(W) Heat Dissipation Characteristics VSON010V3030
[W] 3.0 (3) 3.03W (1) Substrate (copper foil density: 0.2%...1-layer) j-a=178.6/W (2) Substrate (copper foil density: 7%...1-layer) j-a=98.4/W (3) Substrate (copper foil density: 65%...1-layer) j-a=41.3/W
Power Dissipation [Pd]
(2) 1.27W 2.0
1.0
(1) 0.70W
0 0 25 50 75 100 125 150
Ambient Temperature [Ta]
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15/16
2009.04 - Rev.B
BD3540NUV, BD3541NUV
Ordering part number
Technical Note
B
D
3
5
4
0
N
U
V
-
E
2
Part No.
Part No. 3540 , 3541
Package NUV : VSON010V3030
Packaging and forming specification E2: Embossed tape and reel
VSON010V3030
3.00.1
3.00.1

Tape Quantity
S
(0.22)
Embossed carrier tape 3000pcs E2
The direction is the 1pin of product is at the upper left when you hold
1.0MAX
1PIN MARK
0.08 S 2.00.1 0.5
0.40.1
C0.25
1.20.1
1 5
10
6
+0.03 0.02 -0.02
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
0.5
+0.05 0.25 -0.04
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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16/16
2009.04 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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